MFRC522_I2C.h 22 KB

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  1. /**
  2. * MFRC522_I2C.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS I2C BY AROZCAN
  3. * MFRC522_I2C.h - Based on ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI Library BY COOQROBOT.
  4. * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
  5. * Created by Miguel Balboa (circuitito.com), Jan, 2012.
  6. * Rewritten by Søren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
  7. * Extended by Tom Clement with functionality to write to sector 0 of UID changeable Mifare cards.
  8. * Extended by Ahmet Remzi Ozcan with I2C functionality.
  9. * Author: arozcan @ https://github.com/arozcan/MFRC522-I2C-Library
  10. * Released into the public domain.
  11. *
  12. * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
  13. * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
  14. *
  15. * There are three hardware components involved:
  16. * 1) The micro controller: An Arduino
  17. * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
  18. * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
  19. *
  20. * The microcontroller and card reader uses I2C for communication.
  21. * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
  22. *
  23. * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
  24. * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
  25. * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
  26. * Details are found in chapter 6, Type A – Initialization and anticollision.
  27. *
  28. * If only the PICC UID is wanted, the above documents has all the needed information.
  29. * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
  30. * The MIFARE Classic chips and protocol is described in the datasheets:
  31. * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
  32. * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
  33. * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
  34. * The MIFARE Ultralight chip and protocol is described in the datasheets:
  35. * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
  36. * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
  37. *
  38. * MIFARE Classic 1K (MF1S503x):
  39. * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
  40. * The blocks are numbered 0-63.
  41. * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
  42. * Bytes 0-5: Key A
  43. * Bytes 6-8: Access Bits
  44. * Bytes 9: User data
  45. * Bytes 10-15: Key B (or user data)
  46. * Block 0 is read-only manufacturer data.
  47. * To access a block, an authentication using a key from the block's sector must be performed first.
  48. * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
  49. * All keys are set to FFFFFFFFFFFFh at chip delivery.
  50. * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
  51. * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
  52. * MIFARE Classic 4K (MF1S703x):
  53. * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
  54. * The blocks are numbered 0-255.
  55. * The last block in each sector is the Sector Trailer like above.
  56. * MIFARE Classic Mini (MF1 IC S20):
  57. * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
  58. * The blocks are numbered 0-19.
  59. * The last block in each sector is the Sector Trailer like above.
  60. *
  61. * MIFARE Ultralight (MF0ICU1):
  62. * Has 16 pages of 4 bytes = 64 bytes.
  63. * Pages 0 + 1 is used for the 7-byte UID.
  64. * Page 2 contains the last check digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
  65. * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
  66. * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
  67. * MIFARE Ultralight C (MF0ICU2):
  68. * Has 48 pages of 4 bytes = 192 bytes.
  69. * Pages 0 + 1 is used for the 7-byte UID.
  70. * Page 2 contains the last check digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
  71. * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
  72. * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
  73. * Page 40 Lock bytes
  74. * Page 41 16 bit one way counter
  75. * Pages 42-43 Authentication configuration
  76. * Pages 44-47 Authentication key
  77. */
  78. #ifndef MFRC522_h
  79. #define MFRC522_h
  80. #include <Arduino.h>
  81. #include <Wire.h>
  82. // Firmware data for self-test
  83. // Reference values based on firmware version
  84. // Hint: if needed, you can remove unused self-test data to save flash memory
  85. //
  86. // Version 0.0 (0x90)
  87. // Philips Semiconductors; Preliminary Specification Revision 2.0 - 01 August 2005; 16.1 Sefttest
  88. const byte MFRC522_firmware_referenceV0_0[] PROGMEM = {
  89. 0x00, 0x87, 0x98, 0x0f, 0x49, 0xFF, 0x07, 0x19,
  90. 0xBF, 0x22, 0x30, 0x49, 0x59, 0x63, 0xAD, 0xCA,
  91. 0x7F, 0xE3, 0x4E, 0x03, 0x5C, 0x4E, 0x49, 0x50,
  92. 0x47, 0x9A, 0x37, 0x61, 0xE7, 0xE2, 0xC6, 0x2E,
  93. 0x75, 0x5A, 0xED, 0x04, 0x3D, 0x02, 0x4B, 0x78,
  94. 0x32, 0xFF, 0x58, 0x3B, 0x7C, 0xE9, 0x00, 0x94,
  95. 0xB4, 0x4A, 0x59, 0x5B, 0xFD, 0xC9, 0x29, 0xDF,
  96. 0x35, 0x96, 0x98, 0x9E, 0x4F, 0x30, 0x32, 0x8D
  97. };
  98. // Version 1.0 (0x91)
  99. // NXP Semiconductors; Rev. 3.8 - 17 September 2014; 16.1.1 Self test
  100. const byte MFRC522_firmware_referenceV1_0[] PROGMEM = {
  101. 0x00, 0xC6, 0x37, 0xD5, 0x32, 0xB7, 0x57, 0x5C,
  102. 0xC2, 0xD8, 0x7C, 0x4D, 0xD9, 0x70, 0xC7, 0x73,
  103. 0x10, 0xE6, 0xD2, 0xAA, 0x5E, 0xA1, 0x3E, 0x5A,
  104. 0x14, 0xAF, 0x30, 0x61, 0xC9, 0x70, 0xDB, 0x2E,
  105. 0x64, 0x22, 0x72, 0xB5, 0xBD, 0x65, 0xF4, 0xEC,
  106. 0x22, 0xBC, 0xD3, 0x72, 0x35, 0xCD, 0xAA, 0x41,
  107. 0x1F, 0xA7, 0xF3, 0x53, 0x14, 0xDE, 0x7E, 0x02,
  108. 0xD9, 0x0F, 0xB5, 0x5E, 0x25, 0x1D, 0x29, 0x79
  109. };
  110. // Version 2.0 (0x92)
  111. // NXP Semiconductors; Rev. 3.8 - 17 September 2014; 16.1.1 Self test
  112. const byte MFRC522_firmware_referenceV2_0[] PROGMEM = {
  113. 0x00, 0xEB, 0x66, 0xBA, 0x57, 0xBF, 0x23, 0x95,
  114. 0xD0, 0xE3, 0x0D, 0x3D, 0x27, 0x89, 0x5C, 0xDE,
  115. 0x9D, 0x3B, 0xA7, 0x00, 0x21, 0x5B, 0x89, 0x82,
  116. 0x51, 0x3A, 0xEB, 0x02, 0x0C, 0xA5, 0x00, 0x49,
  117. 0x7C, 0x84, 0x4D, 0xB3, 0xCC, 0xD2, 0x1B, 0x81,
  118. 0x5D, 0x48, 0x76, 0xD5, 0x71, 0x61, 0x21, 0xA9,
  119. 0x86, 0x96, 0x83, 0x38, 0xCF, 0x9D, 0x5B, 0x6D,
  120. 0xDC, 0x15, 0xBA, 0x3E, 0x7D, 0x95, 0x3B, 0x2F
  121. };
  122. // Clone
  123. // Fudan Semiconductor FM17522 (0x88)
  124. const byte FM17522_firmware_reference[] PROGMEM = {
  125. 0x00, 0xD6, 0x78, 0x8C, 0xE2, 0xAA, 0x0C, 0x18,
  126. 0x2A, 0xB8, 0x7A, 0x7F, 0xD3, 0x6A, 0xCF, 0x0B,
  127. 0xB1, 0x37, 0x63, 0x4B, 0x69, 0xAE, 0x91, 0xC7,
  128. 0xC3, 0x97, 0xAE, 0x77, 0xF4, 0x37, 0xD7, 0x9B,
  129. 0x7C, 0xF5, 0x3C, 0x11, 0x8F, 0x15, 0xC3, 0xD7,
  130. 0xC1, 0x5B, 0x00, 0x2A, 0xD0, 0x75, 0xDE, 0x9E,
  131. 0x51, 0x64, 0xAB, 0x3E, 0xE9, 0x15, 0xB5, 0xAB,
  132. 0x56, 0x9A, 0x98, 0x82, 0x26, 0xEA, 0x2A, 0x62
  133. };
  134. class MFRC522 {
  135. public:
  136. // MFRC522 registers. Described in chapter 9 of the datasheet.
  137. enum PCD_Register {
  138. // Page 0: Command and status
  139. // 0x00 // reserved for future use
  140. CommandReg = 0x01 , // starts and stops command execution
  141. ComIEnReg = 0x02 , // enable and disable interrupt request control bits
  142. DivIEnReg = 0x03 , // enable and disable interrupt request control bits
  143. ComIrqReg = 0x04 , // interrupt request bits
  144. DivIrqReg = 0x05 , // interrupt request bits
  145. ErrorReg = 0x06 , // error bits showing the error status of the last command executed
  146. Status1Reg = 0x07 , // communication status bits
  147. Status2Reg = 0x08 , // receiver and transmitter status bits
  148. FIFODataReg = 0x09 , // input and output of 64 byte FIFO buffer
  149. FIFOLevelReg = 0x0A , // number of bytes stored in the FIFO buffer
  150. WaterLevelReg = 0x0B , // level for FIFO underflow and overflow warning
  151. ControlReg = 0x0C , // miscellaneous control registers
  152. BitFramingReg = 0x0D , // adjustments for bit-oriented frames
  153. CollReg = 0x0E , // bit position of the first bit-collision detected on the RF interface
  154. // 0x0F // reserved for future use
  155. // Page 1: Command
  156. // 0x10 // reserved for future use
  157. ModeReg = 0x11 , // defines general modes for transmitting and receiving
  158. TxModeReg = 0x12 , // defines transmission data rate and framing
  159. RxModeReg = 0x13 , // defines reception data rate and framing
  160. TxControlReg = 0x14 , // controls the logical behavior of the antenna driver pins TX1 and TX2
  161. TxASKReg = 0x15 , // controls the setting of the transmission modulation
  162. TxSelReg = 0x16 , // selects the internal sources for the antenna driver
  163. RxSelReg = 0x17 , // selects internal receiver settings
  164. RxThresholdReg = 0x18 , // selects thresholds for the bit decoder
  165. DemodReg = 0x19 , // defines demodulator settings
  166. // 0x1A // reserved for future use
  167. // 0x1B // reserved for future use
  168. MfTxReg = 0x1C , // controls some MIFARE communication transmit parameters
  169. MfRxReg = 0x1D , // controls some MIFARE communication receive parameters
  170. // 0x1E // reserved for future use
  171. SerialSpeedReg = 0x1F , // selects the speed of the serial UART interface
  172. // Page 2: Configuration
  173. // 0x20 // reserved for future use
  174. CRCResultRegH = 0x21 , // shows the MSB and LSB values of the CRC calculation
  175. CRCResultRegL = 0x22 ,
  176. // 0x23 // reserved for future use
  177. ModWidthReg = 0x24 , // controls the ModWidth setting?
  178. // 0x25 // reserved for future use
  179. RFCfgReg = 0x26 , // configures the receiver gain
  180. GsNReg = 0x27 , // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
  181. CWGsPReg = 0x28 , // defines the conductance of the p-driver output during periods of no modulation
  182. ModGsPReg = 0x29 , // defines the conductance of the p-driver output during periods of modulation
  183. TModeReg = 0x2A , // defines settings for the internal timer
  184. TPrescalerReg = 0x2B , // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
  185. TReloadRegH = 0x2C , // defines the 16-bit timer reload value
  186. TReloadRegL = 0x2D ,
  187. TCounterValueRegH = 0x2E , // shows the 16-bit timer value
  188. TCounterValueRegL = 0x2F ,
  189. // Page 3: Test Registers
  190. // 0x30 // reserved for future use
  191. TestSel1Reg = 0x31 , // general test signal configuration
  192. TestSel2Reg = 0x32 , // general test signal configuration
  193. TestPinEnReg = 0x33 , // enables pin output driver on pins D1 to D7
  194. TestPinValueReg = 0x34 , // defines the values for D1 to D7 when it is used as an I/O bus
  195. TestBusReg = 0x35 , // shows the status of the internal test bus
  196. AutoTestReg = 0x36 , // controls the digital self test
  197. VersionReg = 0x37 , // shows the software version
  198. AnalogTestReg = 0x38 , // controls the pins AUX1 and AUX2
  199. TestDAC1Reg = 0x39 , // defines the test value for TestDAC1
  200. TestDAC2Reg = 0x3A , // defines the test value for TestDAC2
  201. TestADCReg = 0x3B // shows the value of ADC I and Q channels
  202. // 0x3C // reserved for production tests
  203. // 0x3D // reserved for production tests
  204. // 0x3E // reserved for production tests
  205. // 0x3F // reserved for production tests
  206. };
  207. // MFRC522 commands. Described in chapter 10 of the datasheet.
  208. enum PCD_Command {
  209. PCD_Idle = 0x00, // no action, cancels current command execution
  210. PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
  211. PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
  212. PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
  213. PCD_Transmit = 0x04, // transmits data from the FIFO buffer
  214. PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
  215. PCD_Receive = 0x08, // activates the receiver circuits
  216. PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
  217. PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
  218. PCD_SoftReset = 0x0F // resets the MFRC522
  219. };
  220. // MFRC522 RxGain[2:0] masks, defines the receiver's signal voltage gain factor (on the PCD).
  221. // Described in 9.3.3.6 / table 98 of the datasheet at http://www.nxp.com/documents/data_sheet/MFRC522.pdf
  222. enum PCD_RxGain {
  223. RxGain_18dB = 0x00 << 4, // 000b - 18 dB, minimum
  224. RxGain_23dB = 0x01 << 4, // 001b - 23 dB
  225. RxGain_18dB_2 = 0x02 << 4, // 010b - 18 dB, it seems 010b is a duplicate for 000b
  226. RxGain_23dB_2 = 0x03 << 4, // 011b - 23 dB, it seems 011b is a duplicate for 001b
  227. RxGain_33dB = 0x04 << 4, // 100b - 33 dB, average, and typical default
  228. RxGain_38dB = 0x05 << 4, // 101b - 38 dB
  229. RxGain_43dB = 0x06 << 4, // 110b - 43 dB
  230. RxGain_48dB = 0x07 << 4, // 111b - 48 dB, maximum
  231. RxGain_min = 0x00 << 4, // 000b - 18 dB, minimum, convenience for RxGain_18dB
  232. RxGain_avg = 0x04 << 4, // 100b - 33 dB, average, convenience for RxGain_33dB
  233. RxGain_max = 0x07 << 4 // 111b - 48 dB, maximum, convenience for RxGain_48dB
  234. };
  235. // Commands sent to the PICC.
  236. enum PICC_Command {
  237. // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
  238. PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
  239. PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
  240. PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
  241. PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
  242. PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 2
  243. PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 3
  244. PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
  245. // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
  246. // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
  247. // The read/write commands can also be used for MIFARE Ultralight.
  248. PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
  249. PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
  250. PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
  251. PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
  252. PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
  253. PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
  254. PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
  255. PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
  256. // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
  257. // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
  258. PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
  259. };
  260. // MIFARE constants that does not fit anywhere else
  261. enum MIFARE_Misc {
  262. MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
  263. MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
  264. };
  265. // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
  266. enum PICC_Type {
  267. PICC_TYPE_UNKNOWN = 0,
  268. PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
  269. PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
  270. PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
  271. PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
  272. PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
  273. PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
  274. PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
  275. PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
  276. PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
  277. };
  278. // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
  279. enum StatusCode {
  280. STATUS_OK = 1, // Success
  281. STATUS_ERROR = 2, // Error in communication
  282. STATUS_COLLISION = 3, // Collission detected
  283. STATUS_TIMEOUT = 4, // Timeout in communication.
  284. STATUS_NO_ROOM = 5, // A buffer is not big enough.
  285. STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
  286. STATUS_INVALID = 7, // Invalid argument.
  287. STATUS_CRC_WRONG = 8, // The CRC_A does not match
  288. STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
  289. };
  290. // A struct used for passing the UID of a PICC.
  291. typedef struct {
  292. byte size; // Number of bytes in the UID. 4, 7 or 10.
  293. byte uidByte[10];
  294. byte sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
  295. } Uid;
  296. // A struct used for passing a MIFARE Crypto1 key
  297. typedef struct {
  298. byte keyByte[MF_KEY_SIZE];
  299. } MIFARE_Key;
  300. // Member variables
  301. Uid uid; // Used by PICC_ReadCardSerial().
  302. // Size of the MFRC522 FIFO
  303. static const byte FIFO_SIZE = 64; // The FIFO is 64 bytes.
  304. /////////////////////////////////////////////////////////////////////////////////////
  305. // Functions for setting up the Arduino
  306. /////////////////////////////////////////////////////////////////////////////////////
  307. MFRC522(byte chipAddress);
  308. /////////////////////////////////////////////////////////////////////////////////////
  309. // Basic interface functions for communicating with the MFRC522
  310. /////////////////////////////////////////////////////////////////////////////////////
  311. void PCD_WriteRegister(byte reg, byte value);
  312. void PCD_WriteRegister(byte reg, byte count, byte *values);
  313. byte PCD_ReadRegister(byte reg);
  314. void PCD_ReadRegister(byte reg, byte count, byte *values, byte rxAlign = 0);
  315. void setBitMask(unsigned char reg, unsigned char mask);
  316. void PCD_SetRegisterBitMask(byte reg, byte mask);
  317. void PCD_ClearRegisterBitMask(byte reg, byte mask);
  318. byte PCD_CalculateCRC(byte *data, byte length, byte *result);
  319. /////////////////////////////////////////////////////////////////////////////////////
  320. // Functions for manipulating the MFRC522
  321. /////////////////////////////////////////////////////////////////////////////////////
  322. void PCD_Init();
  323. void PCD_Reset();
  324. void PCD_AntennaOn();
  325. void PCD_AntennaOff();
  326. byte PCD_GetAntennaGain();
  327. void PCD_SetAntennaGain(byte mask);
  328. bool PCD_PerformSelfTest();
  329. /////////////////////////////////////////////////////////////////////////////////////
  330. // Functions for communicating with PICCs
  331. /////////////////////////////////////////////////////////////////////////////////////
  332. byte PCD_TransceiveData(byte *sendData, byte sendLen, byte *backData, byte *backLen, byte *validBits = NULL, byte rxAlign = 0, bool checkCRC = false);
  333. byte PCD_CommunicateWithPICC(byte command, byte waitIRq, byte *sendData, byte sendLen, byte *backData = NULL, byte *backLen = NULL, byte *validBits = NULL, byte rxAlign = 0, bool checkCRC = false);
  334. byte PICC_RequestA(byte *bufferATQA, byte *bufferSize);
  335. byte PICC_WakeupA(byte *bufferATQA, byte *bufferSize);
  336. byte PICC_REQA_or_WUPA(byte command, byte *bufferATQA, byte *bufferSize);
  337. byte PICC_Select(Uid *uid, byte validBits = 0);
  338. byte PICC_HaltA();
  339. /////////////////////////////////////////////////////////////////////////////////////
  340. // Functions for communicating with MIFARE PICCs
  341. /////////////////////////////////////////////////////////////////////////////////////
  342. byte PCD_Authenticate(byte command, byte blockAddr, MIFARE_Key *key, Uid *uid);
  343. void PCD_StopCrypto1();
  344. byte MIFARE_Read(byte blockAddr, byte *buffer, byte *bufferSize);
  345. byte MIFARE_Write(byte blockAddr, byte *buffer, byte bufferSize);
  346. byte MIFARE_Decrement(byte blockAddr, long delta);
  347. byte MIFARE_Increment(byte blockAddr, long delta);
  348. byte MIFARE_Restore(byte blockAddr);
  349. byte MIFARE_Transfer(byte blockAddr);
  350. byte MIFARE_Ultralight_Write(byte page, byte *buffer, byte bufferSize);
  351. byte MIFARE_GetValue(byte blockAddr, long *value);
  352. byte MIFARE_SetValue(byte blockAddr, long value);
  353. /////////////////////////////////////////////////////////////////////////////////////
  354. // Support functions
  355. /////////////////////////////////////////////////////////////////////////////////////
  356. byte PCD_MIFARE_Transceive(byte *sendData, byte sendLen, bool acceptTimeout = false);
  357. // old function used too much memory, now name moved to flash; if you need char, copy from flash to memory
  358. //const char *GetStatusCodeName(byte code);
  359. const __FlashStringHelper *GetStatusCodeName(byte code);
  360. byte PICC_GetType(byte sak);
  361. // old function used too much memory, now name moved to flash; if you need char, copy from flash to memory
  362. //const char *PICC_GetTypeName(byte type);
  363. const __FlashStringHelper *PICC_GetTypeName(byte type);
  364. void PICC_DumpToSerial(Uid *uid);
  365. void PICC_DumpMifareClassicToSerial(Uid *uid, byte piccType, MIFARE_Key *key);
  366. void PICC_DumpMifareClassicSectorToSerial(Uid *uid, MIFARE_Key *key, byte sector);
  367. void PICC_DumpMifareUltralightToSerial();
  368. void MIFARE_SetAccessBits(byte *accessBitBuffer, byte g0, byte g1, byte g2, byte g3);
  369. bool MIFARE_OpenUidBackdoor(bool logErrors);
  370. bool MIFARE_SetUid(byte *newUid, byte uidSize, bool logErrors);
  371. bool MIFARE_UnbrickUidSector(bool logErrors);
  372. /////////////////////////////////////////////////////////////////////////////////////
  373. // Convenience functions - does not add extra functionality
  374. /////////////////////////////////////////////////////////////////////////////////////
  375. bool PICC_IsNewCardPresent();
  376. bool PICC_ReadCardSerial();
  377. private:
  378. byte _chipAddress;
  379. byte _resetPowerDownPin; // Arduino pin connected to MFRC522's reset and power down input (Pin 6, NRSTPD, active low)
  380. byte MIFARE_TwoStepHelper(byte command, byte blockAddr, long data);
  381. };
  382. #endif